Real space transfer (RST) semiconductor devices are known to the art. See, for instance, S. Luryi's chapter in "Heterojunction Band Discontinuities: Physics and Device Applications", F. Capasso et al., editors, Elsevier 1987, especially pages 513-539, incorporated herein by reference.
Known RST devices include a transistor, variously called charge-injection transistor (CHINT) or negative resistance field effect transistor (NERFET), and the hot-electron erasable programmable random access memory (HE.sup.2 PRAM). See, for instance, U.S. Pat. No. 4,903,092, also incorporated herein by reference. Known RST devices also include a recently disclosed novel logic element (See U.S. Pat. No. 4,999,687, incorporated herein by reference), and a recently disclosed light emitting device (See U.S. patent application Ser. No. 716,751 filed Jun. 18, 1991 for S. Luryi; and S. Luryi, Applied Physics Letters, Vol. 58(16), p. 1727; both incorporated herein by reference).
Briefly, RST devices generally are three (or more) terminal devices based on real-space transfer of hot electrons from a first to a second conducting region. The two conducting regions are separated by a barrier region and are contacted independently, with the first conducting region having two (or more) surface contacts (frequently referred to as "source" and "drain"). Application of a source-to-drain bias V.sub.sd can lead to heating of charge carriers in the first region and consequent charge injection into the second conducting region. The first region thus acts as a hot carrier emitter and the second region as a collector. This terminology will generally be used herein.
An important requirement in the implementation of a RST device is electrical insulation between emitter and collector layers. Prior art RST devices have used alloyed source and drain contacts, well known in FET technology. However, when used in RST devices, alloyed source-drain contacts have proven themselves capriciously prone to short circuit across the barrier. RST devices with alloyed source-drain contacts thus would at best be difficult to manufacture.
The above referred-to shorting problem was overcome by means of the epitaxial contacts introduced by P. M. Mensz et al. (Applied Physics Letters, Vol. 56(25), p. 2563). In this technology, contacts are made to an ultra-heavily doped layer (the emitter contact layer), grown epitaxially over the emitter layer. The contacts are made by depositing suitably patterned contact metal onto the contact layer, such that relatively large contact pads are formed. No alloying is required, and the channel length is defined in a separate step by etching a "trench" of width L.sub.ch through the emitter contact layer.
RST devices potentially are very fast, their ultimate performance believed to be limited substantially only by the time of flight of hot carriers (typically electrons) across the barrier layer. However, actual devices have so far fallen short of the potential performance. The main reason for this performance shortfall is associated with the existence of relatively large parasitic capacitances in prior art RST devices. For instance, associated with the above-discussed epitaxial contact devices (Mensz et al., op. cit.; see also C.-T. Liu et al., IEEE Transactions on Electron Devices, Vol. 38(11), p. 2417) is parasitic capacitance between the collector and the areas of the emitter layer outside of the trench.
Recently, "top-collector" RST devices were disclosed. See M. R. Hueschen et al., Applied Physics Letters, Vol. 57(4), p. 386; and K. Maezawa et al., Japanese Journal of Applied Physics, Vol. 30(6), p. 1190. In these devices the lateral extent of the collector is defined by lithography, and can consequently be small. Thus, the above discussed parasitic capacitance can be substantially reduced in such devices. However, the prior art top-collector devices present another problem. As those skilled in the art will appreciate, both source and drain contacts must be self-aligned with the collector, in order to avoid introduction of (speed-degrading) series resistance into the channel. However, alloying of such self-aligned contacts frequently degrades the integrity of the barrier layer, leading to an increase in undesirable parasitic leakage across the barrier.
In view of the many advantageous features of RST devices, including potentially high speed, it would be highly desirable to have available device geometries that can result in devices that are free of, or at least less subject to, some of the shortcomings associated with prior art geometries. This application discloses such devices, and methods for making such devices.